PCIe^® Speeds and Limitations

Peripheral Component Interconnect express (PCIe) SSDs use the PCIe interface to connect directly to the CPU, allowing for faster data transfer rates compared to traditional SATA SSDs. 

If you’re interested in upgrading to PCIe storage, the Crucial System Scanner and Crucial System Advisor will list all compatible M.2 PCIe NVMe SSDs for your system – whether it uses current or earlier revisions of the PCIe standard.

In addition, PCIe systems without M.2 ports can be upgraded with aftermarket adapters which can be installed in earlier standards, or the adapters may comply with those standards themselves. 

Crucial SSDs are backward compatible with these older standards, but if you are seeing lower-than-expected performance, it's important to verify your PCIe revision by reviewing your system or motherboard documentation from the manufacturer.

Older standards, or systems where PCIe interfaces are using fewer data lanes as discussed in BIOS/UEFI Configuration for Optimizing M.2 PCIe NVMe SSDs, will reduce bandwidth and lower performance by at least half.

The table below outlines maximum theoretical current PCIe speeds by both PCIe generation and number of lanes. If you have trouble achieving expected benchmark results for your PCIe devices, remember that due to system overhead and other hardware characteristics, real-world numbers will be about 15% lower, and will not exceed the rated speeds of the storage device itself.

Notes:

• Bandwidth overhead: Indicates the percentage of bandwidth lost to encoding and other protocol overheads.
• Latency: The delay in data transmission, important for real-time applications like gaming or high-frequency trading.
• Scalability issues: Refers to challenges in expanding system capabilities, such as adding more devices without affecting performance.
• Compatibility concerns: Highlights potential issues when different generations of PCIe are used together or when older devices are used with newer PCIe versions.
   

PCIe 6.0 specifications have been finalized and released by PCI-SIG, the consortium responsible for developing the PCI Express standards. Compared to PCIe 5.0, PCIe 6.0 brings significant improvements over previous generations, particularly in terms of bandwidth and efficiency. Here is a summary of the key features and projected capabilities:

1. Bandwidth: PCIe 6.0 doubles the data rate to 64GT/s (Giga transfers per second) per lane, effectively providing up to 256GB/s in each direction on a x16 configuration. This is twice the bandwidth of PCIe 5.0.
2. Encoding: It utilizes PAM-4 (Pulse Amplitude Modulation with 4 levels) encoding, which allows for higher data rates. This is a shift from the NRZ (Non-Return to Zero) encoding used in PCIe 5.0 and earlier.
3. Forward Error Correction (FEC): This feature helps in maintaining data integrity across higher transmission speeds, crucial for reducing the error rate which typically increases with faster speeds.
4. Latency: PCIe 6.0 aims to maintain or reduce latency compared to PCIe 5.0, despite the higher data rates, thanks to more efficient data handling and error correction mechanisms.
5. Backward compatibility: Like previous iterations, PCIe 6.0 is designed to be backward compatible with all previous versions of PCIe, ensuring that existing hardware can still be used with new devices that feature PCIe 6.0 interfaces.

High-end sectors like servers, data centers, and enterprise-level computing are likely to be among the first to adopt PCIe 6.0, followed by consumer electronics such as high-performance gaming PCs and workstations. The adoption timeline can also be influenced by the development of other complementary technologies that benefit from or require the increased bandwidth and capabilities of PCIe 6.0.

PCIe 6.0 is expected to become commercially available from 2024, with broader adoption following in 2025 and beyond.